A non-crystalline oxide is represented by the formula:
ABO4 
wherein A is an element selected from Group IIIA of the periodic table; and B is an element selected from Group VB of the periodic table.
The invention generally relates to oxides that may be used in conjunction with integrated circuit devices, and methods of making the same.
The Semiconductor Industry Association (SIA) National Technology Roadmap for Semiconductors (NTRS) currently projects that gate dielectrics with oxide equivalent thicknesses, (tox,eq), below 1 nm may be potentially desirable for use in complementary metal-semiconductor oxide field-effect transistor (CMOS FET) devices having channel lengths scaled to below 50 nm. Conventional devices may become increasingly undesirable since direct tunneling through silicon dioxide (SiO2) may significantly exceed a nominal limit of approximately 1 A/cm2 at applied gate bias levels of about 1 V above threshold for an oxide equivalent thickness of less than 1.5 nm.
One possible approach for decreasing tox,eq without increasing tunneling leakage current is based on substituting alternative oxides with dielectric constants (k) that could potentially exceed that of SiO2, which has a k value of approximately 3.8. As an example, it would be desirable to obtain oxides with dielectric constants ranging from approximately 10 to 30. Silicon nitride alloys and silicon oxynitride alloys have been proposed as a technology bridge since these materials are believed to have dielectric constants of approximately 7.6 and 5.5 to 6.0 respectively. More specifically, C. J. Parker, G. Lucovsky and J. R. Hauser, IEEE Electron. Device Lett. (1998); Y. Wu and G. Lucovsky, IEEE Electron. Device Lett. (1998); and H. Yang and G. Lucovsky, IEDM Digest, (1999) propose oxide-nitride and oxide-oxynitride alloy stacked dielectrics with tox,eq projected to be greater than about 1.1 nm before tunneling leakage at approximately 1 V is increased above 1 A/cm2. The preparation of these stacked dielectrics proposes two 300xc2x0 C. remote plasma process steps: i) plasma-assisted oxidation to form Si-SiO2 interface layers ranging in thickness from about 0.5 to 6 nm, and ii) remote plasma-enhanced chemical vapor deposition (RPECVD) to deposit either a nitride or an oxynitride (e.g., (SiO2)x(Si3N4)1-x) dielectric film in the dielectric stack. After deposition, a low thermal budget, e.g., 30 second, 900xc2x0 C., rapid thermal anneal (RTA) has been proposed in an attempt to achieve chemical and structural relaxation. This RTA may promote optimized performance in IGFET devices [G. Lucovsky, A. Banerjee, B. Hinds, G. Claflin, K. Koh and H. Yang, J. Vac. Sci. Technol. B15, 107 (1997)]. Stacked nitride and oxynitride gate dielectrics are capable of displaying improved performance and reliability with respect to thermally-grown oxides of the same equivalent thickness. Nonetheless, these gate dielectrics typically should have tox,eq of greater than 1.1 nm in order to attempt to maintain direct tunneling leakage below 1 A/cm2. The nitride and oxynitride layers of these devices may be sufficiently thick to minimize or stop boron out-diffusion out of p+ polycrystalline Si gate electrodes in the p-channel IGFETs [Y. Wu, et al., Vac. Sci. Technol. B17 1813 (1999)].
The use of other high-k dielectrics (e.g., a k greater than 8) has been proposed and includes TiO2 [J. Yan, D. C. Gilmer, S. A. Campbell, W. L. Gladfelter and P. G. Schmid, J. Vac. Sci. Technol. B 14, 1706 (1996).], Ta2O5 [H. Shinrike and M. Nakata, IEEE Trans. on Elec. Devices 38, 544 (1991)], Al2O3 [L. Manchanda, W. H. Lee, J. E. Bower, F. H. Baumann, W. L. Brown, et al., IEDM Tech. Dig., p. 605 (1998)], ZrO2, [R. B. van Dover, et al., IEEE Electron Device Lett., 19, 329, (1998)] and Zr(Hf)O2-SiO2 (also designated as Zr(Hf)-silicates; see van Dover et al.). Notwithstanding any possible benefits, it is generally believed that these materials may not demonstrate the targeted goals of capacitance with decreased tunneling or leakage currents that are desirable for silicon CMOS devices with tox,eq less than 1 nm, and extending to 0.5 nm to 0.6 nm. Although not wishing to be bound by any theory, it is believed that the performance of the materials may be limited due to the oxidation of the silicon substrate that occurs during thermal chemical vapor deposition (CVD) or during post-deposition processing, such as, for example, thermal anneals, to fully oxidize the deposited thin films.
Other potential problems encountered with various high-k dielectrics may relate to: (1) the crystallization of the deposited films during either deposition or post-deposition processing, (2) the low dielectric constants of the bulk films that may be insufficient to meet the targeted goals, and (3) the formation of interfacial silicide bonds, e.g., Si-Ta bonds, during the initial stages of film deposition for an oxide including, for example, Ta2O5. For example, it is believed that oxidation of the silicon substrate during deposition or post-deposition processing may mitigate many of the gains of high-k layers with respect to achievable capacitance, whereas crystallization has the potential to open up alternative conduction pathways, the possibility of anisotropic dielectric constant behavior, and the potential to produce surface roughening.
The formation of interfacial silicide bonds may undesirably result in interfacial defects. Such defects may possibly occur in the form of fixed positive charge or interface traps. Thus, it may be desirable to employ a thin dielectric interface layer of SiO2 between the dielectric layer and the silicon substrate. Utilizing such interfacial layers with known insulating film dielectrics, however, may be disadvantageous in that they may limit the dielectric stacks from having sufficient capacitance to meet the ever-increasing scaling demands of CMOS devices. Additionally, this use of interfacial layers may also limit the incorporation of high-k oxides into devices that employ semiconductor substrates other than silicon such as, for example, silicon carbide, gallium nitride and compound semiconductors such as GaAs, (Al,Ga)As, and (In,Ga)As.
Thus, there is a need in the art for oxides that may be employed as insulating dielectrics in microelectronic devices which may address the above-mentioned problems.
In one aspect, the invention relates to non-crystalline oxides. The non-crystalline oxides are represented by the formula (I):
ABO4 
wherein A is an element selected from Group IIIA of the periodic table and B is an element selected from Group VB of the periodic table.
In another aspect, the invention relates to methods of forming non-crystalline oxides represented by the formula (I). The methods comprise delivering gaseous sources comprising element A, gaseous sources comprising element B, and gaseous sources comprising oxygen on substrates such that the gaseous sources comprising element A, the gaseous sources comprising element B, and the gaseous sources comprising oxygen react to form the non-crystalline oxides. Elements A and B are preferably available in equal amounts required for compositional stoichiometry, and wherein the gaseous sources comprising oxygen preferably contains a sufficient amount of chemically active oxygen such that the elements A and B are completely oxidized.
In another aspect, the invention relates to field effect transistors which employ the non-crystalline oxides represented by the formula (I). The field effect transistors comprise integrated circuit substrates having first surfaces, source and drain regions in the substrates at the first surfaces in spaced apart relationships, and gate insulating layers on the substrates at the first surfaces between the spaced apart source and drain regions. The gate insulating layers comprise non-crystalline oxides represented by the formula (I). Source, drain, and gate contacts are provided to contact the source and drain regions and the gate insulating layer, respectively.
The non-crystalline oxides may be employed in field effect transistors as thin gate insulating layers having high dielectric constants. Advantageously, the non-crystalline oxides potentially allow for field effect transistors employing the same to possess gate capacitance in excess of what may be achieved with conventional insulating layers with significantly reduced direct tunneling currents. As an example, the direct tunneling currents may be reduced from levels in excess of 1 A/cm2.